Technologies for fabricating semiconductor devices, such as transistors, capacitors and the like, for ultra-high density integrated circuits have been developed which extend patterning resolution beyond that of conventional lithography (which is typically limited to about 80 nm pitch). Self-aligned multiple patterning is one such class of high resolution patterning technologies. The current state of the art multiple patterning technology contemplated for commercial production is a method known as Self-Aligned Quadruple Patterning (SAQP), which is an extrapolation of the more commonly commercially used Self-Aligned Double Patterning (SADP) technique. Problematically, however, the theoretical minimum regular pitch (i.e., the minimum distance between repetitive features in a semiconductor device structure) for a SAQP process is about 20 nanometers (nm) using conventional lithographic techniques.
Moreover, formation of interconnect systems having large arrays of multiple parallel metal lines in a Back-End-Of-Line (BEOL) process flow for a semiconductor fabrication often require the metal lines to have both variable pitch and variable line widths. This kind of variability in both pitch and line width is very difficult to achieve with a conventional SAQP process. This is particularly the case when the pitch (i.e., the minimum distance between repetitive features in a semiconductor device structure) is less than or equal to 38 nm.
Typically, an interconnect system located in the back end, or BEOL portion, of a semiconductor structure will be composed of many cells of repetitive arrays of lines, wherein the overall height of each cell is an integer multiple of a minimum pitch, or track. The track (or minimum pitch) being equal to the minimum allowable line width plus the minimum space between the lines. For example, a five track cell in an interconnection system where the minimum pitch is 36 nm would have an overall height that is five times 36 nm, for a total of 180 nm. By way of another example, a six track cell having a minimum pitch of 28 nm would have an overall height of six times 28 nm, for a total of 168 nm.
However, within those cells, different lines will have different functions and, therefore, will require different line widths. For example, power lines within a typical cell are primarily used to deliver power to devices (such as transistors) in a semiconductor structure and signal lines within that same cell are used to carry signals to and from the semiconductor devices. Since the power lines must carry much more current than the signal lines, the power lines must be significantly wider than the signal lines and therefore require a larger pitch. This type of variability is difficult to achieve in an SAQP process. Moreover, other prior art processes that have more flexibility than the SAQP process, such as litho-etch litho-etch (LELE), are subject to lithographic variation problems that make them unreliable at small pitches, such as pitches below 36 nm.
Additionally, if the spaces between metal lines in a cell of a semiconductor interconnect system become too narrow due to, for example, such lithographic variability, those unacceptably small spaces can lead to time delayed shorting between the lines. Time delayed shorting, or Time Delayed Dielectric Breakdown (TDDB), can occur when the spaces between lines become so small that the dielectric isolating material between the lines becomes stressed over an extended period of time by the electric fields being generated between the lines.
Next generation lithographic techniques, such as extreme ultraviolet lithography (EUV), may potentially reduce such conventional lithographic variability. However, such technologies must overcome development problems that currently limit their resolution. For example, it is currently recognized that EUV cannot practically realize a 40 nm pitch or less, due to stochastic effects in resist exposure.
Accordingly, there is a need for an apparatus, and method of forming the same, of cells of an interconnect system for a semiconductor structure, wherein the spaces between lines within the cell are not subject to lithographic variability. Additionally, there is a need for the lines within the cells to be variable in width and variable in pitch. There is a need, specifically, for such variable line widths and pitches where the cells have a track (or minimum pitch between lines) of 36 nm or less.